A phase locked loop has widely been used in the applications such as frequency control, frequency synthesis, FM demodulation, data recovery, signal synchronization or the like.
Further, in one of the application phase locked loop, there is a jitter attenuator which may remove the phase fluctuation, i.e. jitter, caused by superimposed clocks. In this case, it is necessary that the loop bandwidth of the phase locked loop used in the jitter attenuator is narrow as compared with the frequency bandwidth of the jitter to be eliminated. In order to narrow the loop bandwidth, it is most effective to lower the gain of a voltage control oscillating circuit which constitutes the phase locked loop. The voltage control oscillating circuit which lower the gain of phase locked loop can readily be realized if a quartz oscillating circuit constituting the phase locked loop is used.
FIG. 1 is a block diagram illustrating the arrangement of a conventional jitter attenuator phase locked loop using the quartz oscillating circuit (See "JITTER ATTENUATION PHASE LOCKED LOOP USING SWITCHED CAPACITOR CONTROLLED CRYSTAL OSCILLATOR", IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCE).
This phase locked loop is comprised of a phase/frequency detector 92, a flip-flop circuit 93 and a quartz oscillating circuit. Further, the foregoing quartz oscillating circuit is comprised of a quartz-crystal resonator 94, an amplifier circuit 95, load capacitors 100 through 105 and switches 96 through 99 for switching load capacitors 100, 101, 104, 105 respectively. Incidentally, the capacitance of each of the load capacitors 102, 103 is C1, the capacitance of each of the load capacitors 100, 105 is C2 and the capacitance of each of the load capacitors 101, 104 is C3.
The phase/frequency detector 92 compares the phases of a signal IN provided to an input terminal 91 and of an signal REF provided from the quartz oscillating circuit. If the phase of the IN signal is more advanced than that of the REF signal, then it emits a signal LEAD according to that phase difference and, if the phase of the IN signal is more lagged than that of the REF signal, it emits a signal LAG according to that phase difference. The flip-flop circuit 93 operates in synchronism with a clock signal CLOCK and emits a signal UP or DOWN according to the output of the phase/frequency detector 92.
At the quartz oscillating circuit, if the signal UP is provided, then switches 96 through 99 are all turned OFF, and only the load capacitors 102, 103 are electrically connected to both terminals of the quartz-crystal resonator 94. Further, if the signal DOWN is provided, the switches 96 through 99 are all turned ON, and the load capacitors 100 through 105 are electrically connected to both terminals of the quartz-crystal resonator 94. Further, if any one of the signals UP and DOWN is not entered, then the switches 96, 99 are turned ON, and the switches 97, 98 are turned OFF, and the load capacitors 100, 102, 103, 105 are electrically connected to both terminals of the quartz-crystal resonator 94. Since the oscillating frequency of the quartz oscillating circuit depends on the capacitance of the load capacitor connected to the quartz-crystal resonator and is decreased as the capacitance is increased, the oscillating frequency of the quartz oscillating circuit is switched depending on the signals UP and DOWN given from the flip-flop circuit 93. Therefore, if the output of this quartz oscillating circuit is fed back to the phase/frequency detector 92, then a phase locked loop can be formed.
Incidentally, the phase locked loop of FIG. 1 is comprised of the phase/ferquency detector 92, flip-flop circuit 93 and oscillating circuit only, and has no portion corresponding to a loop filter. That is, with this phase locked loop, the order of the loop is one. With such a first order phase locked loop, it is known that the bandwidth of the loop is determined by only the loop gain. In consequence, in the circuit of FIG. 1, the bandwidth of the loop will be determined by only the gain of the quartz oscillating circuit.
However, the foregoing conventional phase locked suffers the following problems.
That is, since the gain of the quartz oscillating circuit is determined by the equivalent circuit of the quartz-crystal resonator and the load capacitance, its resulting gain suffers a certain limit of itself, and a desired loop bandwidth often cannot be obtained. In other words, with the conventional phase locked loop, because of the first order loop, the degree of freedom is small when the loop bandwidth is determined.
Further, with the first order phase locked loop, when a difference arises between the input signal frequency and the central frequency of the oscillating circuit, a steady phase error can be generated in proportion to the frequency offset. With the jitter attenuator, it is necessary to use a FIFO (First-in, First-out) which writes in synchronism with the input of the phase locked loop while reading in synchronism with the output. However, if the steady phase error takes place to the phase locked loop, then it becomes necessary to use the additional FIFO stage corresponding to the phase error. Therefore, it is necessary to predict how far the frequency error will occur so that the FIFO having the additional stage number corresponding to that frequency error may be available.
The present invention was conceived in view of the foregoing circumstances, and its object is to provide a phase locked loop in which the freedom of choice of the loop bandwidth is large and which may prevent the steady phase error relative to the frequency offset from being generated.